FIG. 8 depicts a memory system comprising two DRAMs (dynamic random access memories) 800a, 800b as well as a memory controller 801. Memory controller 801 as well as DRAMs 800a, 800b are connected via signal lines transmitting the signals DQ[c] and DQ[d]. Signals DQ[c], DQ[d] are connected to input and/or output circuits of memory controller 801 as well as of DRAMs 800a, 800b. FIG. 8 depicts a diagrammatic representation of a point to two-point connection (P22P), as is expected, for example, for a DDR3 databus. FIG. 8 depicts two input and output circuits, respectively, both for memory controller 801 and for DRAMs 800a, 800b. Each of these input and output circuits comprises an input buffer 804, 804′, 836, 836′, an output buffer 834, 834′, 838, 838′, a termination resistor RTT as well as an output drive strength RON. An output drive strength is marked by RON. For evaluating the signals DQ[c], DQ[d] received, input buffers 804, 804′, 836, 836′ are connected both to signals DQ[c], DQ[d] and to an external reference voltage signal VREF_ext generated by a reference voltage generator 832′. Evaluation is effected by comparing a signal voltage of signals DQ[c], DQ[d] to a reference voltage provided by the reference voltage signal VREF_ext.
If the signal voltage exceeds the reference voltage, a first logical value is detected; if the signal voltage falls short of the reference voltage, however, a second logical value is detected and provided by input buffers 804, 804′, 836, 836′ to DRAMs 800a, 800b, or to memory controller 801. The lines of signals DQ[c], DQ[d] are terminated, in DRAMs 800a, 800b and in the memory controller 801, via termination resistors RTT with a termination voltage which is provided by a termination signal VTT_ext to DRAMs 800a, 800b as well as to memory controller 801, and is generated by a termination voltage generator 833′. Signals DQ[c], DQ[d] are bidirectional signals driven by output buffers 834, 834′, 838, 838′. Signals DQ[c], DQ[d] are chosen by way of example. Memory controller 801 as well as DRAMs 800a, 800b usually comprise a multiplicity of further signal input and output circuits which, however, are not depicted for reasons of clarity.
Instead of the reference voltage supply provided by reference voltage generator 832′, a reference voltage supply may be effected, alternatively, individually per chip, for example using separate reference voltage generators or internal reference voltage generation on each chip.
In a write case, data is transmitted via data signals DQ[c], DQ[d] from memory controller 801 with RON as the output drive strength to one or both DRAMs 800a, 800b, each of which comprises the termination resistor RTT. Such a write case will be described by way of example in the figures below. However, this does not represent a limitation, since the write case described may be transferred to any kind of data transfer with different possibilities of combining output drive circuits, termination circuits and input receiving circuits.
As data rates on interface buses of memory chips increase, for example signals DQ[c], DQ[d], shown in FIG. 8, between memory controller 801 and DRAMs 800a, 800b, the requirements placed on the interface circuits of the memory components in terms of accuracy are also on the increase. The requirements in terms of accuracy may be categorized by the type of interface circuits such as output driver, input receiver, termination circuits, i.e., in FIG. 8 input buffers 804, 804′, 836, 836′, output buffers 834, 834′, 838, 838′ as well as termination resistors RTT. In addition, the requirements in terms of accuracy may be categorized by the type of requirements, such as accuracy of resistances, voltage ranges, timing requirements or load capacities.
A potential combination of accuracy requirements may be as follows, for example:
output driver (off-chip driver, OCD):                output impedance: 40Ω+/−10%        output timing accuracy, tDQSQ, tQHS, tAC, tDQSCK: +/−125 picoseconds . . . +/−150 picoseconds        parasitic capacitance at IO pin (sum of all IO circuits and housings): 2 . . . 3 Pf        
input receiving circuit (receiver, RCV):                Vin AC: Vref+/−200 mV        Vin DC: Vref+/−100 mV        Vref: 1.05 V+/−40 mV        
termination circuit (on-die termination, ODT):                termination resistor RTT: 60Ω or 120Ω+/−10%        termination voltage VTT: 1.5 V+/−75 mV        
FIGS. 9 and 10 show simulated data eyes 912, 1012 of data signals DQ[c], DQ[d] shown in FIG. 8. FIG. 9 shows the simulated data eye 912 at the input amplifiers of the two DRAMs shown in FIG. 8, at nominally set RON and RTT values and at a termination voltage VTT of 1.5 V. Termination voltage VTT is provided by the termination voltage generator depicted in FIG. 8. The data signal shown alternates between an upper voltage value 912a at about 1.5 V and a lower voltage value 912b at about 0.6 V. The two voltage values 912a, 912b correspond to two signal states which are referred to as “high” and “low” and designate the value of a data bit transmitted. The data eye is symmetrical in relation to a reference voltage VREF=1.05 V assumed to be nominal. Reference voltage VREF is generated, in FIG. 8, by the reference voltage generator. The case depicted in FIG. 9 is ideal, since identical conditions apply to both signal states 912a, 912b. In this and in subsequent figures, an intersymbol interference (ISI) is defined as a width of a crossing area of the data eye and reference voltage VREF. In the ideal case depicted in FIG. 9, the ISI has a width of 30 picoseconds. An output driver resistor RON_CTRL has a value of 40 ohms, and a termination resistor has a value of 120 ohms.
FIG. 10 shows data eye 1012 for the event that an output driver has a slightly lower resistance, and that a termination resistor has a slightly higher resistance in comparison with the embodiment shown in FIG. 9. Instead of the nominal values in FIG. 9, in FIG. 10, the output drive strength RON=0.9*RON_nom, and the termination resistor RTT=1.1*RTT_nom. Termination voltage VTT continues to be 1.5 V. As a result, only the low level 1012b at the input amplifiers of the two DRAMs is shifted from about 0.6 V in FIG. 9 to 0.5 V in FIG. 10. The high level 1012a remains unchanged at about 1.5 V. This causes a crossing point ISI′ of the data eye of signal 1012 to no longer coincide with reference voltage VREF=1.05 V, but to go down. Hereby, a time available to the input amplifiers for recognizing a logical 1 is reduced. This expressed by ISI′ measured at the reference voltage value of 1.05 V. It increases from about 30 picoseconds in FIG. 9 to about 50 picoseconds. An output drive resistor RON_CTRL has a value of 36 ohms and a termination resistor has a value of 132 ohms.
The shift of the data eye, described with reference to FIG. 10, relative to reference voltage VREF occurs especially when termination voltage VTT nominally is set to a different value than reference voltage VREF. This is the case, for example, with new memory interfaces. With GDDR3 (graphics DDR3), termination voltage VTT, for example, equals 1.8 V, and reference voltage VREF=1.26 V. With the future standard for DDR3 commodity DRAMs, what is currently expected is VTT=1.5 V, and VREF=1.05 V.
FIG. 11 depicts an increase in the ISI discussed with reference to FIGS. 9 and 10, measured at a nominal reference voltage VREF_nom=1.05 V, depicted as ISI_sim_Vref_nom as a function of an opposite parameter variation of RON and RTT. At RON=0.8*RON_nom and RTT=1.2*RTT_nom the ISI increases to about 80 picoseconds as against 30 picoseconds in the nominal case. In addition, FIG. 11 shows that with deviations of about +/−20% or +/−30%, a simple approximation formula may be used for calculating the ISI. If an input slew rate of 2.4 V/ns is assumed at the input amplifiers (this value matching the data eye depicted in FIG. 9), an additionally occurring ISI may be calculated using a slope triangle consisting of voltage, time and slew rate, as is depicted as ISI_cal—2.4 V/ns in FIG. 11.
Thus, FIG. 11 allows the conclusion that a maximally admissible deviation from the nominal value at RON and RTT must be limited to +/−10% so as to limit any occurring ISI to about 65 picoseconds, with nominal VREF.
With current memory-interface standards such as DDR2 or GDDR3, the above accuracy requirements are met in that the output drivers and/or the termination resistors are adjustable, within certain limits, on the chip. By corresponding calibration routines, the actual values of these resistors in the system are approximated to the nominal value as far as possible.
With DDR2, a calibration in the system is performed by the memory controller. This is disadvantageous since it requires a time-consuming calibration protocol as well as complex implementation. In addition, the chip pins have a high capacitance caused by a fine-tunability of the drive strength RON.
With GDDR3, the chips in the system are auto-calibrated. This is disadvantageous since highly accurate, external or possibly also internal reference resistors are required. In addition, the chip pins have a high capacitance caused by a fine-tunability of drive strength RON and termination strength RTT.